There are two general categories of flash memories, namely, EPROMs (Erasable Programmable ROMs) and EEPROMs (Electrically Erasable Programmable ROMs). The program and erase operation of an EPROM is performed by charging or discharging its floating gate with ultraviolet rays or X-rays. However, the programming and erase operation of an EEPROM is performed by electrically charging or discharging its floating gate. EEPROMs can be readily updated, even when embedded into a system. Therefore, EEPROMs are employed in many different systems. EEPROMs are generally divided into two categories, namely, a byte removal type and a flash type. The flash type of EEPROMS may again be divided into two types, namely, a hot-electron injection type and an F—N(Fowler-Nordgein) current type.
FIG. 1 is a cross-sectional view illustrating a conventional method for fabricating a floating gate of a flash memory device.
EEPROMs generally store one bit using a transistor. As shown in FIG. 1, such a flash memory device comprises a tunnel gate oxide layer formed on a silicon substrate, a floating gate, an insulating layer on the floating gate (which functions as an isolation layer), and a control gate.
Typically, the voltage for the program and erase operation is applied to the control gate. The voltage applied to the control gate is determined according to the coupling ratio. The coupling ratio is the ratio of the voltage applied to the floating gate to the voltage applied to the control gate. The initial voltage applied to the control gate must be higher than the voltage required to change the state of the floating gate for the program and erase operation to be initiated. Thus, the efficiency of the program and erase operation increases in proportion to the coupling ratio.
Various methods have been provided to increase the coupling ratio. One of the known methods is to enlarge the coupling area between the floating gate and the control gate. For example, in some known methods the floating gate is formed to have a convexo-concave () shape which has a larger area than a plane and, thus, enlarges the coupling area. As a result of this known approach, various methods have been provided to form the sidewalls of the floating gate into convexo-concave() shapes.
FIG. 2 through FIG. 4 are cross-sectional views illustrating a known method for fabricating a floating gate of a flash memory device as described in Wu, Korean Patent No. 0,376,863.
Referring to FIG. 2, a first oxide layer 3 is formed on an area 2 doped with impurities in a substrate 1. A first nitride layer 4 is then deposited on the first oxide layer 3. A second oxide layer 5 is then formed on the first nitride layer 4. A second nitride layer 6 is then deposited on the second oxide layer 5. The convexo-concave() shaped structures are then completed. Next, the gaps between the convexo-concave() shaped structures are filled with a material to form floating gates.
Referring to FIG. 3, the second oxide layer 5, and the first and the second nitride layers 4, 6 in the convexo-concave() shaped structures are removed by an anisotropic etching process. The floating gates 7 are, thus, completed and have a convexo-concave() shape.
Referring to FIG. 4, an ONO (Oxide/Nitride/Oxide) layer or an oxide layer 8 is deposited on the floating gates 7. Control gates 9 are then completed through later processes.
Wang et al., U.S. Pat. No. 6,242,303, describe a method for manufacturing an erasable programmable memory by enlarging the coupling area between the control gate and the floating gate and increasing the capacitive-coupling ratio.
Lee et al., U.S. Pat. No. 5,801,415, describe a method for making an improved electrically programmable ROM device having non volatile memory cells with enhanced capacitive coupling.
Huang, U.S. Pat. No. 5,637,896, describes a process for fabricating an array of floating gate memory devices on a substrate.
The above-mentioned conventional methods for fabricating a floating gate of a flash memory device have several problems. For example, many layers such as the first oxide layer 3, the first nitride layer 4, the second oxide layer 5, and the second nitride layer 6 are required to form the convexo-concave() shapes. This requirement results in complexity and cumbersomeness during all of the processes. Second, as the number of the convexo-concave() shapes increases in order to enlarge the coupling area, the number of processes for depositing insulating layers such as oxide layers or nitride layers may be increased as well. Moreover, the anisotropic process for forming the convexo-concave() shape may cause serious defects in the resulting flash memory devices.